1. Field of the Invention
The present invention relates generally to integrated circuit architecture and more particularly to memory arrays.
2. Background of the Invention
The continuing trend of size reduction of semiconductor memory components in products such as dynamic random access memory (DRAM) has led to development of vertical trench storage capacitors and more recently, vertical access transistors. Both of these devices are associated with the basic unit of a DRAM, the memory cell. An example of a DRAM cell based on a vertical access transistor is disclosed in U.S. Pat. No. 5,519,236. Use of a vertical trench capacitor and a vertical access transistor facilitates the fabrication of a semiconductor memory cell where F=70 nm or less, while at the same time making it possible to maintain the performance of the access transistor.
In order to fabricate the above-described structures, parallel-running active webs that are filled with silicon are formed in an appropriate process, with bulk source and drain electrodes of the FET access transistors located in the webs. At each end, a web is bounded by a deep trench storage capacitor. A gate strip, which forms a gate electrode of each access transistor, is formed on the face of each active web by a vertically etched spacer, which spacer itself is used as a word line for an associated semiconductor memory cell. Gate contacts, the so-called CS (contact to the source) contacts, produce contact with a word line. Furthermore, bit lines run parallel to one another and intersect the word lines and the active webs to which they are fitted essentially at right angles.
When producing wafers for conventional transistor arrays, previously it has been known to integrate a diagnosis test structure in the wafer, which was used for checking the reliability of the access transistors, for detection of the fault density and for capacitance measurement between word lines relative to other layers, and for capacitance measurement between bit lines and relative to other layers.
In memory arrays based on vertical access transistors and vertical trenches as described above (VM), the fabrication processes and architecture are novel, and conventional diagnostic structures may not be suited for measurement of such VM arrays. It is nevertheless desirable to be able to make diagnostic measurements of VM arrays. It will therefore be appreciated that there is a need to improve the ability to measure properties of a VM DRAM.